Patent · US Active

Dual-slice architectures for programmable logic devices

US7675321B1 · kind B1 · utility

1Cited by

9References

18Claims

0Family size

Assignee

Lattice Semiconductor Corporation · US

Inventors

Om P. Agrawal · Los Altos, US
Xiaojie He · Austin, US
Sajitha Wijesuriya · Macungie, US
Barry Britton · Orefield, US
Ming H. Ding · San Jose, US
Jun Zhao · Mianyang, CN

Key dates

Filing date	Mar 24, 2009
Grant date	Mar 9, 2010
Priority date	—
Expiry date	Mar 24, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17728
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

In one embodiment of the invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within a programmable logic block. A dual-slice logic block includes a first slice including at least two lookup tables (LUTs); a second slice including at least two LUTs; and a routing circuit coupled to each of the LUTs within the first and second slices. The routing circuit is adapted to share outputs of the dual-slice logic block among the LUTs. In another embodiment of the invention, the dual-slice logic block includes a second routing circuit coupled to each of the LUTs within the first and second slices. The second routing circuit is adapted to share inputs of the dual-slice logic block among the LUTs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.