High reliable and low power static random access memory
US7679972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2007 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Nov 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.