Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array
US7684264B2 · kind B2 · utility
6Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Feb 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.