Three-terminal non-volatile memory element with hybrid gate dielectric
US7687797B1 · kind B1 · utility
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17References
14Claims
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Key dates
| Filing date | Aug 24, 2005 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Aug 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.