Integrated circuit memory having dynamically adjustable read margin and method therefor
US7688656B2 · kind B2 · utility
4Cited by
21References
21Claims
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Key dates
| Filing date | Oct 22, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Apr 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, including a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.