Method for improved planarization in semiconductor devices
US7696094B2 · kind B2 · utility
4Cited by
2References
17Claims
0Family size
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Key dates
| Filing date | Dec 27, 2006 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Dec 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric material may be planarized using a ceria-based slurry and using the silicon oxynitride mask layer as a stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.