Patent · US Active

NMOS transistors that mitigate fermi-level pinning by employing a hafnium-silicon gate electrode and high-k gate dieletric

US7696517B2 · kind B2 · utility

6Cited by
15References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 25, 2008
Grant dateApr 13, 2010
Priority date—
Expiry dateMay 20, 2028

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/038
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Transistors having a Hafnium-Silicon gate electrode and high-k dielectric are disclosed. A workpiece is provided having a gate dielectric formed over the workpiece, and a gate formed over the gate dielectric. The gate may comprise a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.