Scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval
US7698707B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2008 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Oct 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.