Patent · US Active

Integrated circuit with Resistivity changing memory cells and methods of operating the same

US7706201B2 · kind B2 · utility

13Cited by

5References

24Claims

0Family size

Assignees

Qimonda AG · DE
Altis Semiconductor, SNC · FR

Inventors

Corvin Liaw · Birkenfeld, DE
Michael Angerbauer · Freutsmoos, DE
Peter Schroegmeier · Birkenfeld, DE

Key dates

Filing date	Jul 16, 2007
Grant date	Apr 27, 2010
Priority date	—
Expiry date	Mar 3, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C2213/79
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first and second input terminals; a signal line connected to the memory cells, the reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. A method of operating the integrated circuit includes closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first and second voltages using the voltage comparator, wherein the first voltage represents a memory state of a memory cell, and the second voltage is a reference voltage which represents a memory state of a reference cell, or vice versa.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.