Method and apparatus for optimizing a gate channel
US7713758B2 · kind B2 · utility
15Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2007 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Dec 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.