Method of forming high density trench FET with integrated Schottky diode

US7713822B2 · kind B2 · utility

Assignee

• FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

• Paul Thorup · Hillsboro, US
• Ashok Challa · Sandy, US
• Bruce D. Marchant · Murray, US

Key dates

• Filing date: Oct 10, 2008
• Grant date: May 11, 2010
• Expiry date: Oct 10, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/117

Abstract

A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions. An interconnect layer is formed filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer. The interconnect layer electrically contacts the second silicon region so as to form a Schottky contact therebetween.