Apparatus and method for selectively implementing launch off scan capability in at speed testing
US7721170B2 · kind B2 · utility
5Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Jul 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.