Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
US7723186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Feb 16, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/943
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.