Trench MOSFET with an ONO insulating layer sandwiched between an ESD protection module atop and a semiconductor substrate
US7728385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2009 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Jul 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
A device structure is disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process was found to cause the gate oxide damage before. The present invention structure includes a semiconductor substrate having an active area and a termination area; numerous trench MOSFET cells disposed in the active area; numerous electrostatic discharge (ESD) diodes disposed above the semiconductor substrate in the termination area; and an insulation layer comprising Oxide/Nitride/Oxide (ONO) sandwiched between the ESD diodes and the semiconductor substrate. In one embodiment, the active area does not contain the ONO insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.