Patent · US Active

Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions

US7732291B2 · kind B2 · utility

0Cited by

3References

9Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Joe Bloomquist · Dresden, DE
Peter Javorka · Radebeul, DE
Manfred Horstmann · Dresden, DE
Gert Burbach · Dresden, DE

Key dates

Filing date	Dec 8, 2006
Grant date	Jun 8, 2010
Priority date	—
Expiry date	Jun 19, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/038
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.