Patent · US Active

Etch singulated semiconductor package

US7732899B1 · kind B1 · utility

7Cited by
316References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 4, 2009
Grant dateJun 8, 2010
Priority date
Expiry dateFeb 4, 2029

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/181
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.