Semiconductor wiring structures including dielectric cap within metal cap layer
US7732924B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2007 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Nov 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.