Patent · US Active

Passivation of semiconductor structures having strained layers

US7736935B2 · kind B2 · utility

7Cited by

7References

15Claims

0Family size

Assignee

S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES · FR

Inventors

Bruce Faure · Grenoble, FR
Pascal Guenard · Meylan, FR

Key dates

Filing date	Dec 22, 2008
Grant date	Jun 15, 2010
Priority date	—
Expiry date	Dec 24, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH10H20/84
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The present invention provides, in part, methods producing multilayer semiconductor structures having one or more at least partially relaxed strained layers, where the strained layer is at least partially relaxed by annealing. In particular, the invention forms diffusion barriers that prevent diffusion of contaminants during annealing. The invention also includes embodiments where the at least partially relaxed strained layer is patterned into islands by etching trenches and the like. The invention also provides semiconductor structures resulting from these methods, and further, provides such structures where the semiconductor materials are suitable for application to LED devices, laser devices, photovoltaic devices, and other optoelectronic devices.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.