Resist trim process to define small openings in dielectric layers

US7737021B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Srikanteswara Dakshina-Murthy · Wappingers Falls, US
• Paul R. Besser · Sunnyvale, US
• Jonathan B. Smith · Fremont, US
• Eric M. Apelgren · Austin, US
• Christian Zistl · Dresden, DE
• Jeremy I. Martin · Austin, US
• Lie Zhao · Lake Oswego, US
• Nicholas J. Kepler · San Jose, US

Key dates

• Filing date: Sep 30, 2002
• Grant date: Jun 15, 2010
• Expiry date: Jul 3, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31144
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.