Air gap spacer formation

US7741663B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Fred N. Hause · Austin, US
• Anthony Mowry · Kyle, US
• David Gerald Farber · Plano, US
• Markus Lenski · Dresden, DE

Key dates

• Filing date: Oct 24, 2008
• Grant date: Jun 22, 2010
• Expiry date: Oct 24, 2028

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.