Method of optimizing sidewall spacer size for silicide proximity with in-situ clean
US7745337B2 · kind B2 · utility
1Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2008 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Aug 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.