Methods and apparatus for a memory device with self-healing reference bits
US7747926B2 · kind B2 · utility
8Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2006 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Dec 17, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.