Step height reduction between SOI and EPI for DSO and BOS integration
US7749829B2 · kind B2 · utility
5Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2007 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Feb 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor process and apparatus provides a planarized hybrid substrate (16) by removing a nitride mask layer (96) and using an oxide polish stop layer (92) when an epitaxial semiconductor layer (99) is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack (11) is formed which includes one or more oxide polish stop layers (91, 92) formed between the SOI semiconductor layer (90) and a nitride mask layer (93). The oxide polish stop layer (92) may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.