Trench memory with self-aligned strap formed by self-limiting process
US7749835B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Jun 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.