Stacked integrated circuit package system
US7750454B2 · kind B2 · utility
20Cited by
10References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Mar 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer, and mounting a top integrated circuit package over the intermediate integrated circuit package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.