Reducing transistor junction capacitance by recessing drain and source regions

US7754556B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Thomas Feudel · Radebeul, DE
• Markus Lenski · Dresden, DE
• Andreas Gehring · Dresden, DE

Key dates

• Filing date: Feb 7, 2008
• Grant date: Jul 13, 2010
• Expiry date: May 17, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.