Integrated circuit using FinFETs and having a static random access memory (SRAM)

US7754560B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• James D. Burnett · Austin, US
• Leo Mathew · Austin, US
• Byoung W. Min · Austin, US

Key dates

• Filing date: Jan 10, 2006
• Grant date: Jul 13, 2010
• Expiry date: Jan 14, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).