Patent · US Active

Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone

US7755110B2 · kind B2 · utility

131Cited by

19References

24Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Jorg Gliese · Munich, DE
Winfried Kamp · Munich, DE
Siegmar Koppe · Laatzen, DE
Michael Scheppler · Gröbenzell, DE

Key dates

Filing date	Mar 24, 2005
Grant date	Jul 13, 2010
Priority date	—
Expiry date	Aug 25, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/907
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.