Memory controller granular read queue dynamic optimization of command selection
US7761669B2 · kind B2 · utility
4Cited by
4References
7Claims
0Family size
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Key dates
| Filing date | Jul 10, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Jul 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.