Method and structure for forming a shielded gate field effect transistor
US7767524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2009 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Oct 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.