Methods for fabricating MOS devices having highly stressed channels
US7767534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Sep 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
Abstract
Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.