Nested and isolated transistors with reduced impedance difference
US7767577B2 · kind B2 · utility
0Cited by
2References
18Claims
0Family size
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Key dates
| Filing date | Feb 14, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Sep 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.