Load address dependency mechanism system and method in a high frequency, low power processor system
US7769985B2 · kind B2 · utility
1Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Apr 17, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.