Semiconductor device containing a buried threshold voltage adjustment layer and method of forming
US7772073B2 · kind B2 · utility
24Cited by
6References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Oct 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.