Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region
US7772077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Jul 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.