Reliability of wide interconnects

US7776737B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Griselda Bonilla · Hopewell Junction, US
• Kaushik Chanda · Fishkill, US
• Ronald G. Filippi · Wappingers Falls, US
• Stephan Grunow · Poughkeepsie, US
• Sujatha Sankaran · New Paltz, US
• Andrew H. Simon · Fishkill, US
• Theodorus E. Standaert · Clifton Park, US

Key dates

• Filing date: Aug 14, 2008
• Grant date: Aug 17, 2010
• Expiry date: Feb 5, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.