Design structure for shutting off data capture across asynchronous clock domains during at-speed testing
US7779375B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2007 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Sep 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto; wherein the deactivation mechanism is configured to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the first plurality of latches to downstream latches with respect thereto during at-speed testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.