Device and method for etching flash memory gate stacks comprising high-k dielectric
US7780862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2006 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Dec 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.