DFN semiconductor package having reduced electrical resistance
US7781265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2009 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Mar 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual flat non-leaded semiconductor package is disclosed. A method of making a dual flat non-leaded semiconductor package includes forming a leadframe having a die bonding area with an integral drain lead, a gate lead bonding area and a source lead bonding area, the gate lead bonding area and a source lead bonding area being of increased area; bonding a die to the die bonding area; coupling a die source bonding area to the source lead bonding area; coupling a die gate bonding area to the gate lead bonding area; and partially encapsulating the die, the drain lead, the gate lead and the source lead to form the dual flat non-leaded semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.