CMOS imager array with recessed dielectric
US7781781B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2006 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Nov 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8053
Abstract
A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.