Manufacturing method for forming an integrated circuit device and corresponding integrated circuit device
US7785935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2007 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Jun 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a manufacturing method for forming an integrated circuit device and to a corresponding integrated circuit device. The manufacturing method for forming an integrated circuit device comprises the steps of: forming a first level on a substrate; forming a second level above the first level; forming a cap layer on the second level which covers a first region of the level and leaves a second region uncovered; and simultaneously etching a first contact hole in the first region and a second contact hole in the second region such that the etching is selective to the cap layer in the second region and proceeds to a greater depth in the first region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.