Inventor · Dresden, DE

Marco Lepper

8Patents

2h-index

17Co-inventors

40Inventor score

Filing activity: Nov 13, 2007 → Dec 14, 2015

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8293605B2	Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL)	Electricity	2	Active
US7785935B2	Manufacturing method for forming an integrated circuit device and corresponding integrated circuit device	Electricity	2	Active
US9023696B2	Method of forming contacts for devices with multiple stress liners	Electricity	2	Active
US9023709B2	Top corner rounding by implant-enhanced wet etching	Electricity	1	Active
US9590056B2	Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers	Electricity	1	Active
US9269809B2	Methods for forming protection layers on sidewalls of contact etch stop layers	Electricity	0	Active
US8883586B2	Mol insitu Pt rework sequence	Electricity	0	Active
US8673696B2	SOI semiconductor device comprising a substrate diode with reduced metal silicide leakage	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.