Patent · US Active

Method and apparatus of stress relief in semiconductor structures

US7786007B2 · kind B2 · utility

0Cited by

8References

18Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Mark Hoinkis · Fishkill, US
Matthias Hierlemann · Fishkill, US
Gerald Friese · Munich, DE
Andy Cowley · Wappingers Falls, US
Dennis J. Warner · Mechanicsville, US
Erdem Kaltalioglu · Newburgh, US

Key dates

Filing date	Apr 7, 2008
Grant date	Aug 31, 2010
Priority date	—
Expiry date	Nov 6, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/12044
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.