Stackable semiconductor chip layer comprising prefabricated trench interconnect vias
US7786562B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jun 10, 2005 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Apr 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.