Method and structure for forming multiple self-aligned gate stacks for logic devices

US7790541B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• Advanced Micro Devices, Inc. · US

Inventors

• Bruce B. Doris · Brewster, US
• Mahender Kumar · Hopewell Junction, US
• Werner Rausch · Hopewell Junction, US
• Robin Van Den Nieuwenhuizen · Ridgefield, US

Key dates

• Filing date: Dec 4, 2007
• Grant date: Sep 7, 2010
• Expiry date: Jan 15, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0188

Abstract

A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.