Compensating for layout dimension effects in semiconductor device modeling
US7793240B2 · kind B2 · utility
3Cited by
1References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 29, 2006 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Jan 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.