Method for manufacturing semiconductor package
US7795139B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2007 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Oct 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.