Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same
US7804118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2009 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Dec 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.