Low power circuit structure with metal gate and high-k dielectric

US7807525B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Bruce B. Doris · Brewster, US
• Eduard A. Cartier · New York, US
• Barry P. Linder · Hastings-on-Hudson, US
• Vijay Narayanan · New York, US
• Vamsi K. Paruchuri · New York, US

Key dates

• Filing date: Aug 10, 2009
• Grant date: Oct 5, 2010
• Expiry date: Aug 10, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.