Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)
US7816240B2 · kind B2 · utility
13Cited by
4References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2007 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | May 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.